【產通社，10月13日訊】聯華電子消息，其與全球半導體設計制造軟件暨IP領導廠商——新思科技(Synopsys)已擴展伙伴關系，將于聯華電子28nm HLP Poly SiON制程平臺上開發(fā)新思科技的DesignWare IP。延續(xù)之前在聯華電子40nm與55nm制程的成功經驗，新思科技將會于聯華電子28nm HLP Poly SiON制程上，導入其經驗證的DesignWare嵌入式內存，以及邏輯組件數據庫。此次合作將芯片設計公司得以在較低的風險下，設計出高速低功耗的系統(tǒng)單芯片，并取得更快的產品上市時程。兩家公司長久以來的合作，涵跨了聯華電子0.18微米至28nm制程，而成功研發(fā)出的高質量DesignWare IP，正是這份穩(wěn)固合作關系下的豐碩成果。

聯華電子的28nm HLP制程除了保留傳統(tǒng)Poly SiON技術的成本競爭力，更采用了創(chuàng)新的制程技術，具備絕佳的性價比，與業(yè)界其他28nm Poly SiON制程相比較，大幅提升了效能與功耗表現。此一強化的28nm Poly SiON制程，提供芯片設計者由40nm制程到28nm制程更順暢的移轉路徑，使芯片設計能夠輕易地導入制程并且快速上市。

“聯華電子與新思科技已在多個制程世代上，緊密配合了許多年，”聯華電子負責客戶工程暨硅智財研發(fā)設計支持的簡山杰副總表示，“新思科技是值得信賴的硅智財領導廠商，我們與新思科技在28nm上繼續(xù)攜手，意味著雙方在協(xié)助客戶發(fā)展尖端系統(tǒng)單芯片設計上的共同承諾。聯華電子十分期待與我們的客戶共同將這些新世代產品推出上市�！�

新思科技廣泛的產品組合，包含了經速度，功耗與位面積優(yōu)化，并經過10億顆以上芯片驗證的嵌入式內存與標準組件數據庫。DesignWare嵌入式內存與邏輯組件數據庫包括了先進的電源管理功能，例如淺待機，深待機與關機，還有一個電源優(yōu)化套件，藉以延長手持式應用產品的電池壽命。此外，新思科技整合型STAR Memory System測試與修復解決方案，可讓芯片設計公司達到更高測試質量與嵌入式內存良率，同時降低芯片面積。

“新思科技與晶圓專工領導者聯華電子此次攜手合作，將使雙方客戶得以采用聯華電子28nm制程驗證過的硅智財，用來差異化其系統(tǒng)單芯片的設計�！毙滤伎萍脊柚秦斉c系統(tǒng)營銷副總經理John Koeter表示�！拔覀冊谔峁┫冗M制程的高質量硅智財上，有著豐富經驗與紀錄，因此能給予芯片設計公司信心，在整合DesisnWare IP到系統(tǒng)單芯片設計時，可降低風險，并可望達成首次試產即成功之目標。”

支持聯華電子28nm HLP制程的新思科技DesignWare嵌入式內存與邏輯組件數據庫，預計于2012年第二季推出。新思科技的晶圓專工硅智財支持項目中的部分內容，包含了于聯華電子28nmHLP制程平臺上，免費提供嵌入式內存與邏輯組件數據庫給合乎資格的獲授權者使用。

聯華電子的28nm Poly SiON技術現已在客戶產品試產中，并可接受客戶design-in。查詢進一步信息，請訪問http://www.umc.com。

About DesignWare IP
Synopsys is a leading provider of high-quality, silicon-proven IP solutions for SoC designs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and Verification IP for widely used protocols, analog IP, embedded memories, logic libraries and ARC™ processor cores. In addition, Synopsys offers SystemC™ transaction-level models to build virtual prototypes for rapid, pre-silicon development of software. With a robust IP development methodology, reuse tools, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate time-to-market and reduce integration risk. For more information on DesignWare IP, visit: http://www.synopsys.com/designware. Follow us on Twitter at http://twitter.com/designware_ip.

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.

Forward Looking Statements
This press release contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933 and Section 21E of the Securities Exchange Act of 1934, including statementsregarding the reduced risk, improved time to market, higher test quality and yield, lower chip area, and dates of delivery of embedded memories and logic libraries, and the DesignWare  USB 3.0, USB 2.0, DDR3/2, and PCI Express 2.0 PHYs. These statements are based on current expectations and beliefs. Actual results could differ materially from those described by these statements due to risks and uncertainties including, but not limited to, unforeseen production or delivery delays, failure to perform as expected, and other risks detailed in Synopsys’ filings with the U.S. Securities and Exchange Commission, including those described in the “Risk Factors” section of the latest Quarterly Report on Form 10-Q for the fiscal quarter ended April 30, 2011.