電源噪聲會影響時鐘的性能。本白皮書分析了導致電源噪聲的各種噪聲源，介紹了測量電源噪聲的各種技巧，以及從源頭清除噪聲進而改善系統(tǒng)性能的方法。

August 4, 2011
Power Supply Noise and Clock Generator
Cypress Semiconductor
By Brijesh A Shah

Cypress clock generators are designed to produce low clock noise. Solutions to improve system power supply noise to reduce the clock noise are explained. There are different system noise sources that affect clock generator performance. A practical method to measure power supply noise is explained in the following sections. System power supply noise may cause damage to the system: performance in several ways
. Excess radiated EMI
. Excess conducted EMI
. Excess phase noise and jitter, leading to lower CNR and added BER in transmission systems
. System crashes and inconsistent behavior
. Radiated and conducted EMI tests are required for product sales. It is possible to avoid these problems by designing proper filtering into the system.

System performance also stands important. For data transmission systems, designers are worried about the bit errors induced by the clocking system. Cleaner clocks and better clock phase noise are essential for reducing bit error rate (BER). Because the electronic systems move to higher data rates, minimizing the clock noise becomes important in achieving better system performance.
Clock noise also affects system BER. High BER results in more resent packets, lower system capacity, lower system performance, less margin, and higher service and maintenance costs. Lowering system noise to increase system performance is a key to market success.

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Testing your system, correcting layouts, and improving bypassing for noisy circuit sections are important. The goal is to start with the cleanest system possible by curing noise at the generating source. It is easier and inexpensive to fix a noise source. It is more difficult to harden everything else in the system to protect them from interference.
A system has other noise sources and points of entry for noise into the clocking system than this simple example. The clock generator, clock buffers, interconnects, and clock loads are all entry points for VDD induced phase noise. To discover the source of the noise, use the spectrum analyzer method explained earlier. For successful system design, it is important to measure your system performance. Find the noise sources that show up in the clock phase noise, and clean them up at the source. 查詢進一步信息，請訪問http://www.cypress.com/?docID=30681