AN10798 DisplayPort PCB layout guidelines

關(guān)鍵詞：DisplayPort, PTN33xx, CBTL061xx, PCB, 布線, 信號(hào)完整性, 對(duì)稱(chēng), 損耗, 抖動(dòng)
Keywords DisplayPort, PTN33xx, CBTL061xx, PCB, layout, signal integrity, symmetry, loss, jitter

摘要：本文為采用DisplayPort ICs的電子系統(tǒng)應(yīng)用的PCB設(shè)計(jì)提供了一個(gè)實(shí)用的規(guī)則。
Abstract This document provides a practical guideline for incorporating the DisplayPort ICs layout into PCB designs.

1. Introduction

This document provides a practical guideline for incorporating the NXP DisplayPort (DP) ICs, DisplayPort level shifter PTN33xx family and DP/PCI Express (PCIe) multiplexer CBTL061xx family, layout into a Printed-Circuit Board (PCB) design.

DisplayPort interconnect is a point-to-point layout of serial differential signal trace pairs. The document provides guidelines for DP lane connection for the PCB traces, vias and AC coupling capacitors. The most important considerations are to minimize loss and jitter, and to maintain signal integrity. These are general guidelines only. Board designers should carefully weigh design trade-offs and use simulation analysis to ensure a successful implementation.

2. DisplayPort interconnection PCB layout

DisplayPort is a scalable digital display interface. The interface is designed to support both internal chip-to-chip and external box-to-box digital display connections. The Main Link consists of one, two or four AC-coupled, doubly terminated differential pairs (lanes). Two link rates are supported: 2.7 Gbit/s and 1.62 Gbit/s per lane.

DisplayPort transmit signals are often implemented to share pins with DVI and HDMI signals. These multi-mode DisplayPort signals are sometimes multiplexed with PCI Express signals, which supports 2.5 Gbit/s and/or 5 Gbit/s data rate.

The high bit rate for DP/PCIe requires some specific PCB design considerations. Minimizing interconnect loss and jitter are the key requirements.

了解AN10798原文，請(qǐng)?jiān)L問(wèn)http://www.nxp.com/documents/application_note/AN10798.pdf。